2022-07-10 19:35:50 -05:00
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# SPDX-License-Identifier: GPL-2.0-or-later
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# Cadence virtual debug interface
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# for Palladium emulation systems
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#
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source [find interface/vdebug.cfg]
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# vdebug select JTAG transport
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transport select jtag
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# JTAG reset config, frequency and reset delay
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reset_config trst_and_srst
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adapter speed 50000
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adapter srst delay 5
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2024-01-18 18:10:26 -06:00
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# Future improvement: Enable backdoor memory access
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# set _MEMSTART 0x00000000
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# set _MEMSIZE 0x100000
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# BFM hierarchical path and input clk period
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vdebug bfm_path Testbench.VJTAG 10ns
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# DMA Memories to access backdoor (up to 4)
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# vdebug mem_path tbench.u_mcu.u_sys.u_itcm_ram.Mem $_MEMSTART $_MEMSIZE
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# Create Xtensa target first
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source [find target/xtensa.cfg]
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# Configure Xtensa core parameters next
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# Generate [xtensa-core-XXX.cfg] via "xt-gdb --dump-oocd-config"
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