2022-06-12 16:48:05 -05:00
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# SPDX-License-Identifier: GPL-2.0-or-later
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Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface
- write speed up to 150 kByte/s on STM32F469I-disco (due to
SWD clock and USB connection), up to 1 MByte/s on Nucleo-F767ZI
with external STLink-V3 or Nucleo-G474RE with two W25Q256FV in
dual 4-line mode or STM32H73BI-Disco in octal mode
- tested with STM32L476G-disco (64MBit flash, 3-byte addr),
STM32F412G-Disco, STM32F469I-Disco, STM32F746G-Disco, and
STM32L476G-Disco (all 128Mbit flash, 3-byte addr),
STM32F723E-Disco, STM32F769I-Disco (512Mbit flash, 4-byte addr)
STM32L4R9I-Disco, STM32L4P5G-Disco (512MBit octo-flash, DTR, 4-byte addr)
STM32H745I-Disco, STM32H747I-Disco (two 512MBit flash, 4-byte addr)
STM32H73BI-Disco, STM32H735G-Disco (512MBit octo-flash, DTR, 4-byte addr)
- suitable cfg for Discovery boards included
- limited parsing of SFDP data if flash device not hardcoded
(tested only in single/quad mode as most devices either don't
support SFDP at all or have empty(!) SFDP memory)
- 'set' command for auto detection override (e. g. for EEPROMs)
- 'cmd' command for arbitrary SPI commands (reconfiguration, testing etc.)
- makefile for creation of binary loader files
- tcl/board/stm32f469discovery.cfg superseded by stm32f469i-disco.cfg
- tcl/board/stm32f7discovery.cfg removed as name is ambiguous
(superseded by stm32f746g-disco.cfg vs. stm32f769i-disco.cfg)
- dual 4-line mode tested on Nucleo-F767ZI, Nucleo-H743ZI and Nucleo-H7A3ZI-Q
with two W25Q256FV, and on Nucleo-L496ZP-P and Nucleo-L4R5ZI
with two W25Q128FV, sample cfg files included and on STM32H745I-Disco,
STM32H747I-Disco, STM32H750B-Disco
- read/verify/erase_check uses indirect read mode to work around silicon bug in
H7, L4+ and MP1 memory mapped mode (last bytes not readable, accessing last
bytes causes debug interface to hang)
- octospi supported only in single/dual 1-line, 2-line, 4-line
and single 8-line modes, (not in hyper flash mode)
Requirements:
GPIOs must be initialized appropriately, and SPI flash chip be configured
appropriately (1-line ..., QPI, 4-byte addresses ...). This is board/chip
specific, cf. included cfg files. The driver infers most parameters from
current setting in CR, CCR, ... registers.
Change-Id: I54858fbbe8758c3a5fe58812e93f5f39514704f8
Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-on: http://openocd.zylin.com/4321
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Christopher Head <chead@zaber.com>
2016-12-21 03:35:58 -06:00
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# This is an STM32F412G discovery board with a single STM32F412ZGT6 chip.
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# http://www.st.com/en/evaluation-tools/32f412gdiscovery.html
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# This is for using the onboard STLINK
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source [find interface/stlink.cfg]
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transport select hla_swd
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# increase working area to 128KB
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set WORKAREASIZE 0x20000
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# enable stmqspi
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set QUADSPI 1
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source [find target/stm32f4x.cfg]
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# QUADSPI initialization
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proc qspi_init { } {
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global a
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mmw 0x40023830 0x000000FF 0 ;# RCC_AHB1ENR |= GPIOAEN-GPIOHEN (enable clocks)
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mmw 0x40023838 0x00000002 0 ;# RCC_AHB3ENR |= QSPIEN (enable clock)
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sleep 1 ;# Wait for clock startup
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# PB02: CLK, PG06: BK1_NCS, PF06: BK1_IO3, PF07: BK1_IO2, PF09: BK1_IO1, PF08: BK1_IO0
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# PB02:AF09:V, PF09:AF10:V, PF08:AF10:V, PF07:AF09:V, PF06:AF09:V, PG06:AF10:V
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# Port B: PB02:AF09:V
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mmw 0x40020400 0x00000020 0x00000010 ;# MODER
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mmw 0x40020408 0x00000030 0x00000000 ;# OSPEEDR
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mmw 0x40020420 0x00000900 0x00000600 ;# AFRL
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# Port F: PF09:AF10:V, PF08:AF10:V, PF07:AF09:V, PF06:AF09:V
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mmw 0x40021400 0x000AA000 0x00055000 ;# MODER
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mmw 0x40021408 0x000FF000 0x00000000 ;# OSPEEDR
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mmw 0x40021420 0x99000000 0x66000000 ;# AFRL
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mmw 0x40021424 0x000000AA 0x00000055 ;# AFRH
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# Port G: PG06:AF10:V
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mmw 0x40021800 0x00002000 0x00001000 ;# MODER
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mmw 0x40021808 0x00003000 0x00000000 ;# OSPEEDR
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mmw 0x40021820 0x0A000000 0x05000000 ;# AFRL
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mww 0xA0001030 0x00001000 ;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
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mww 0xA0001000 0x03500008 ;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
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mww 0xA0001004 0x00170100 ;# QUADSPI_DCR: FSIZE=0x17, CSHT=0x01, CKMODE=0
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mmw 0xA0001000 0x00000001 0 ;# QUADSPI_CR: EN=1
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# 1-line spi mode
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mww 0xA0001014 0x000003F5 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO
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sleep 1
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# memory-mapped read mode with 3-byte addresses
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mww 0xA0001014 0x0D002503 ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
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}
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$_TARGETNAME configure -event reset-init {
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mww 0x40023C00 0x00000003 ;# 3 WS for 96 MHz HCLK
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sleep 1
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mww 0x40023804 0x24001808 ;# 96 MHz: HSI, PLLM=8, PLLN=96, PLLP=2
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mww 0x40023808 0x00001000 ;# APB1: /2, APB2: /1
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mmw 0x40023800 0x01000000 0x00000000 ;# PLL on
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sleep 1
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mmw 0x40023808 0x00000002 0x00000000 ;# switch to PLL
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sleep 1
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adapter speed 4000
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qspi_init
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}
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