riscv-openocd/tcl/target/ti_k3.cfg

# SPDX-License-Identifier: GPL-2.0-or-later
# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
#
# Texas Instruments K3 devices:
# * AM243: https://www.ti.com/lit/pdf/spruim2
#  Has 4 R5 Cores, M4F and an M3
# * AM263: https://www.ti.com/lit/pdf/spruj17
#  Has 4 R5 Cores and an M3
# * AM273: https://www.ti.com/lit/pdf/spruiu0
#  Has 2 R5 Cores and an M3
# * AM625: https://www.ti.com/lit/pdf/spruiv7a
#  Has 4 ARMV8 Cores and 1 R5 Core and an M4F
# * AM62A7: https://www.ti.com/lit/pdf/spruj16a
#  Has 4 ARMV8 Cores and 2 R5 Cores
# * AM62P: https://www.ti.com/lit/pdf/spruj83
#  Has 4 ARMV8 Cores and 2 R5 Cores
# * AM642: https://www.ti.com/lit/pdf/spruim2
#  Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3
# * AM654x: https://www.ti.com/lit/pdf/spruid7
#  Has 4 ARMV8 Cores and 2 R5 Cores and an M3
# * J7200: https://www.ti.com/lit/pdf/spruiu1
#  Has 2 ARMV8 Cores and 4 R5 Cores and an M3
# * J721E: https://www.ti.com/lit/pdf/spruil1
#  Has 2 ARMV8 Cores and 6 R5 Cores and an M3
# * J721S2: https://www.ti.com/lit/pdf/spruj28
#  Has 2 ARMV8 Cores and 6 R5 Cores and an M4F
# * J784S4/AM69: http://www.ti.com/lit/zip/spruj52
#  Has 8 ARMV8 Cores and 8 R5 Cores
#

source [find target/swj-dp.tcl]

if { [info exists SOC] } {
	set _soc $SOC
} else {
	set _soc am654
}

# set V8_SMP_DEBUG to non 0 value in board if you'd like to use SMP debug
if { [info exists V8_SMP_DEBUG] } {
	set _v8_smp_debug $V8_SMP_DEBUG
} else {
	set _v8_smp_debug 0
}

# Common Definitions

# System Controller is the very first processor - all current SoCs have it.
set CM3_CTIBASE		{0x3C016000}

# sysctrl power-ap unlock offsets
set _sysctrl_ap_unlock_offsets {0xf0 0x44}
set _sysctrl_ap_num 7

# All the ARMV8s are the next processors.
#		   CL0,CORE0  CL0,CORE1  CL1,CORE0  CL1,CORE1
set ARMV8_DBGBASE {0x90410000 0x90510000 0x90810000 0x90910000}
set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000}

# And we add up the R5s
#		(0)MCU 0   (1)MCU 1   (2)MAIN_0_0 (3)MAIN_0_1 (4)MAIN_1_0 (5)MAIN_1_1
set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000}
set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000}
set R5_NAMES {mcu_r5.0 mcu_r5.1 main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
set _r5_ap_num 1

# Finally an General Purpose(GP) MCU
set CM4_CTIBASE		{0x20001000}

# General Purpose MCU (M4) may be present on some very few SoCs
set _gp_mcu_cores 0
# General Purpose MCU power-ap unlock offsets
set _gp_mcu_ap_unlock_offsets {0xf0 0x60}

# Generic mem-ap port number
set _mem_ap_num 2

# Set configuration overrides for each SOC
switch $_soc {
	am263 {
		set _K3_DAP_TAPID 0x2bb7d02f

		# Mem-ap port
		set _mem_ap_num 6

		# AM263 has 0 ARMV8 CPUs
		set _armv8_cores 0

		# AM263 has 2 cluster of 2 R5s cores.
		set _r5_cores 4
		set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
		set R5_DBGBASE {0x90030000 0x90032000 0x90050000 0x90052000}
		set R5_CTIBASE {0x90038000 0x90039000 0x90058000 0x90059000}
		set _r5_ap_num 5
	}
	am273 {
		set _K3_DAP_TAPID 0x1bb6a02f

		# Mem-ap port
		set _mem_ap_num 6

		# system controller is on AP0
		set _sysctrl_ap_num 0

		# AM273 has 0 ARMV8 CPUs
		set _armv8_cores 0

		# AM273 has 1 cluster of 2 R5s cores.
		set _r5_cores 2
		set R5_NAMES {main0_r5.0 main0_r5.1}
		set R5_DBGBASE {0x90030000 0x90032000}
		set R5_CTIBASE {0x90038000 0x90039000}
		set _r5_ap_num 5
	}
	am654 {
		set _K3_DAP_TAPID 0x0bb5a02f

		# AM654 has 2 clusters of 2 A53 cores each.
		set _armv8_cpu_name a53
		set _armv8_cores 4

		# AM654 has 1 cluster of 2 R5s cores.
		set _r5_cores 2
		set R5_NAMES {mcu_r5.0 mcu_r5.1}

		# Sysctrl power-ap unlock offsets
		set _sysctrl_ap_unlock_offsets {0xf0 0x50}
	}
	am243 -
	am642 {
		set _K3_DAP_TAPID 0x0bb3802f

		# AM642 has 1 clusters of 2 A53 cores each.
		set _armv8_cpu_name a53
		set _armv8_cores 2
		set ARMV8_DBGBASE {0x90010000 0x90110000}
		set ARMV8_CTIBASE {0x90020000 0x90120000}

		# AM642 has 2 cluster of 2 R5s cores.
		set _r5_cores 4
		set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
		set R5_DBGBASE {0x9d410000 0x9d412000 0x9d510000 0x9d512000}
		set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000}

		# M4 processor
		set _gp_mcu_cores 1

		# Overrides for am243
		if { "$_soc" == "am243" } {
			# Uses the same JTAG ID
			set _armv8_cores 0
		}
	}
	am625 {
		set _K3_DAP_TAPID 0x0bb7e02f

		# AM625 has 1 clusters of 4 A53 cores.
		set _armv8_cpu_name a53
		set _armv8_cores 4
		set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000}
		set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000}

		# AM625 has 1 cluster of 1 R5s core.
		set _r5_cores 1
		set R5_NAMES {main0_r5.0}
		set R5_DBGBASE {0x9d410000}
		set R5_CTIBASE {0x9d418000}

		# sysctrl CTI base
		set CM3_CTIBASE {0x20001000}
		# Sysctrl power-ap unlock offsets
		set _sysctrl_ap_unlock_offsets {0xf0 0x78}

		# M4 processor
		set _gp_mcu_cores 1
		set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}

		# Setup DMEM access descriptions
		# DAPBUS (Debugger) description
		set _dmem_base_address 0x740002000
		set _dmem_ap_address_offset 0x100
		set _dmem_max_aps 10
		# Emulated AP description
		set _dmem_emu_base_address 0x760000000
		set _dmem_emu_base_address_map_to 0x1d500000
		set _dmem_emu_ap_list 1
	}
	am62p -
	am62a7 {
		set _K3_DAP_TAPID 0x0bb8d02f

		# AM62a7/AM62P has 1 cluster of 4 A53 cores.
		set _armv8_cpu_name a53
		set _armv8_cores 4
		set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000}
		set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000}

		# AM62a7/AM62P has 2 cluster of 1 R5 core.
		set _r5_cores 2
		set R5_NAMES {main0_r5.0 mcu0_r5.0}
		set R5_DBGBASE {0x9d410000 0x9d810000}
		set R5_CTIBASE {0x9d418000 0x9d818000}

		# sysctrl CTI base
		set CM3_CTIBASE {0x20001000}
		# Sysctrl power-ap unlock offsets
		set _sysctrl_ap_unlock_offsets {0xf0 0x78}

		# Overrides for am62p
		if { "$_soc" == "am62p" } {
			set _K3_DAP_TAPID 0x0bb9d02f
			set R5_NAMES {wkup0_r5.0 mcu0_r5.0}
		}
	}
	j721e {
		set _K3_DAP_TAPID 0x0bb6402f
		# J721E has 1 cluster of 2 A72 cores.
		set _armv8_cpu_name a72
		set _armv8_cores 2

		# J721E has 3 clusters of 2 R5 cores each.
		set _r5_cores 6

		# Setup DMEM access descriptions
		# DAPBUS (Debugger) description
		set _dmem_base_address 0x4c40002000
		set _dmem_ap_address_offset 0x100
		set _dmem_max_aps 8
		# Emulated AP description
		set _dmem_emu_base_address 0x4c60000000
		set _dmem_emu_base_address_map_to 0x1d600000
		set _dmem_emu_ap_list 1
	}
	j7200 {
		set _K3_DAP_TAPID 0x0bb6d02f

		# J7200 has 1 cluster of 2 A72 cores.
		set _armv8_cpu_name a72
		set _armv8_cores 2

		# J7200 has 2 clusters of 2 R5 cores each.
		set _r5_cores 4
		set R5_DBGBASE {0x9d010000 0x9d012000 0x9d110000 0x9d112000}
		set R5_CTIBASE {0x9d018000 0x9d019000 0x9d118000 0x9d119000}

		# M3 CTI base
		set CM3_CTIBASE {0x20001000}
	}
	j721s2 {
		set _K3_DAP_TAPID 0x0bb7502f

		# J721s2 has 1 cluster of 2 A72 cores.
		set _armv8_cpu_name a72
		set _armv8_cores 2

		# J721s2 has 3 clusters of 2 R5 cores each.
		set _r5_cores 6

		# sysctrl CTI base
		set CM3_CTIBASE {0x20001000}
		# Sysctrl power-ap unlock offsets
		set _sysctrl_ap_unlock_offsets {0xf0 0x78}

		# M4 processor
		set _gp_mcu_cores 1
		set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
	}
	j784s4 {
		set _K3_DAP_TAPID 0x0bb8002f

		# j784s4 has 2 cluster of 4 A72 cores each.
		set _armv8_cpu_name a72
		set _armv8_cores 8
		set ARMV8_DBGBASE {0x90410000 0x90510000 0x90610000 0x90710000
                           0x90810000 0x90910000 0x90a10000 0x90b10000}
		set ARMV8_CTIBASE {0x90420000 0x90520000 0x90620000 0x90720000
                           0x90820000 0x90920000 0x90a20000 0x90b20000}

		# J721s2 has 4 clusters of 2 R5 cores each.
		set _r5_cores 8
		set R5_DBGBASE {0x9d010000 0x9d012000
                        0x9d410000 0x9d412000
                        0x9d510000 0x9d512000
                        0x9d610000 0x9d612000}
		set R5_CTIBASE {0x9d018000 0x9d019000
                        0x9d418000 0x9d419000
                        0x9d518000 0x9d519000
                        0x9d618000 0x9d619000}
		set R5_NAMES {mcu_r5.0 mcu_r5.1
                      main0_r5.0 main0_r5.1
                      main1_r5.0 main1_r5.1
                      main2_r5.0 main2_r5.1}

		# sysctrl CTI base
		set CM3_CTIBASE {0x20001000}
		# Sysctrl power-ap unlock offsets
		set _sysctrl_ap_unlock_offsets {0xf0 0x78}
	}
	default {
		echo "'$_soc' is invalid!"
	}
}

proc _get_rtos_type_for_cpu { target_name } {
	if { [info exists ::RTOS($target_name)] } {
		return $::RTOS($target_name)
	}
	return none
}

set _CHIPNAME $_soc

swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version

dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu

set _TARGETNAME $_CHIPNAME.cpu

set _CTINAME $_CHIPNAME.cti

# sysctrl is always present
cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap \
	-ap-num $_sysctrl_ap_num -baseaddr [lindex $CM3_CTIBASE 0]

target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap \
	-ap-num $_sysctrl_ap_num -defer-examine \
	-rtos [_get_rtos_type_for_cpu $_TARGETNAME.sysctrl]

$_TARGETNAME.sysctrl configure -event reset-assert { }

proc sysctrl_up {} {
	# To access sysctrl, we need to enable the JTAG access for the same.
	# Ensure Power-AP unlocked
	$::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 0] 0x00190000
	$::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 1] 0x00102098

	$::_TARGETNAME.sysctrl arp_examine
}

$_TARGETNAME.sysctrl configure -event gdb-attach {
	sysctrl_up
	# gdb-attach default rule
	halt 1000
}

proc _cpu_no_smp_up {} {
	set _current_target [target current]
	set _current_type [$_current_target cget -type]

	$_current_target arp_examine
	$_current_target $_current_type dbginit
}

proc _armv8_smp_up {} {
	for { set _core 0 } { $_core < $::_armv8_cores } { incr _core } {
		$::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
		$::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
		$::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on
	}
	# Set Default target as core 0
	targets $::_TARGETNAME.$::_armv8_cpu_name.0
}

set _v8_smp_targets ""

for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {

	cti create $_CTINAME.$_armv8_cpu_name.$_core -dap $_CHIPNAME.dap -ap-num 1 \
		-baseaddr [lindex $ARMV8_CTIBASE $_core]

	target create $_TARGETNAME.$_armv8_cpu_name.$_core aarch64 -dap $_CHIPNAME.dap -coreid $_core \
		-dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine \
		-rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_armv8_cpu_name.$_core]

	set _v8_smp_targets "$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core"

	if { $_v8_smp_debug == 0 } {
		$_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
			_cpu_no_smp_up
			# gdb-attach default rule
			halt 1000
		}
	} else {
		$_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
			_armv8_smp_up
			# gdb-attach default rule
			halt 1000
		}
	}
}

if { $_armv8_cores > 0 } {
	# Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs
	set _armv8_up_cmd "$_armv8_cpu_name"_up
	# Available if V8_SMP_DEBUG is set to non-zero value
	set _armv8_smp_cmd "$_armv8_cpu_name"_smp

	if { $_v8_smp_debug == 0 } {
		proc $_armv8_up_cmd { args } {
			foreach _core $args {
				targets $_core
				_cpu_no_smp_up
			}
		}
	} else {
		proc $_armv8_smp_cmd { args } {
			_armv8_smp_up
		}
		# Declare SMP
		target smp {*}$_v8_smp_targets
	}
}

for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
	set _r5_name [lindex $R5_NAMES $_core]
	cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num $_r5_ap_num \
		-baseaddr [lindex $R5_CTIBASE $_core]

	# inactive core examination will fail - wait till startup of additional core
	target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
		-dbgbase [lindex $R5_DBGBASE $_core] -ap-num $_r5_ap_num -defer-examine \
		-rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_r5_name]

	$_TARGETNAME.$_r5_name configure -event gdb-attach {
		_cpu_no_smp_up
		# gdb-attach default rule
		halt 1000
	}
}

proc r5_up { args } {
	foreach  _core $args {
		targets $_core
		_cpu_no_smp_up
	}
}

if { $_gp_mcu_cores != 0 } {
	cti create $_CTINAME.gp_mcu -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0]
	target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine \
		-rtos [_get_rtos_type_for_cpu $_TARGETNAME.gp_mcu]
	$_TARGETNAME.gp_mcu configure -event reset-assert { }

	proc gp_mcu_up {} {
		# To access GP MCU, we need to enable the JTAG access for the same.
		# Ensure Power-AP unlocked
		$::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 0] 0x00190000
		$::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 1] 0x00102098

		$::_TARGETNAME.gp_mcu arp_examine
	}

	$_TARGETNAME.gp_mcu configure -event gdb-attach {
		gp_mcu_up
		# gdb-attach default rule
		halt 1000
	}
}

# In case of DMEM access, configure the dmem adapter with offsets from above.
if { 0 == [string compare [adapter name] dmem ] } {
	if { [info exists _dmem_base_address] } {
		# DAPBUS (Debugger) description
		dmem base_address $_dmem_base_address
		dmem ap_address_offset $_dmem_ap_address_offset
		dmem max_aps $_dmem_max_aps

		# The following are the details of APs to be emulated for direct address access.
		# Debug Config (Debugger) description
		dmem emu_base_address_range $_dmem_emu_base_address $_dmem_emu_base_address_map_to
		dmem emu_ap_list $_dmem_emu_ap_list
		# We are going local bus, so speed is really dummy here.
		adapter speed 2500
	} else {
		puts "ERROR: ${SOC} data is missing to support dmem access!"
	}
} else {
	# AXI AP access port for SoC address map
	target create $_CHIPNAME.axi_ap mem_ap -dap $_CHIPNAME.dap -ap-num $_mem_ap_num
}