riscv-openocd/tcl/fpga/altera-cyclonev.cfg

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# SPDX-License-Identifier: GPL-2.0-or-later
# Intel Cyclone 5 FPGA
# see Cyclone V Device Handbook
# Table 9-1: IDCODE Information for Cyclone V Devices
#5CEA2 0x02b150dd
#5CEA4 0x02b050dd
#5CEA5 0x02b220dd
#5CEA7 0x02b130dd
#5CEA9 0x02b140dd
#5CGXC3 0x02b010dd
#5CGXC4 0x02b120dd
#5CGXC5 0x02b020dd
#5CGXC7 0x02b030dd
#5CGXC9 0x02b040dd
#5CGTD5 0x02b020dd
#5CGTD7 0x02b030dd
#5CGTD9 0x02b040dd
#5CSEA2 0x02d110dd
#5CSEA4 0x02d010dd
#5CSEA5 0x02d120dd
#5CSEA6 0x02d020dd
#5CSXC2 0x02d110dd
#5CSXC4 0x02d010dd
#5CSXC5 0x02d120dd
#5CSXC6 0x02d020dd
#5CSTD5 0x02d120dd
#5CSTD6 0x02d020dd
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME cyclonev
}
jtag newtap $_CHIPNAME tap -irlen 10 \
-expected-id 0x02b150dd -expected-id 0x02b050dd \
-expected-id 0x02b220dd -expected-id 0x02b130dd \
-expected-id 0x02b140dd -expected-id 0x02b010dd \
-expected-id 0x02b120dd -expected-id 0x02b020dd \
-expected-id 0x02b030dd -expected-id 0x02b040dd \
-expected-id 0x02d110dd -expected-id 0x02d010dd \
-expected-id 0x02d120dd -expected-id 0x02d020dd
pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cyclonev