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riscv-openocd/tcl/board/kasli.cfg

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tcl: replace command "interface" with "adapter driver" Avoid annoying "deprecated" messages while running the scripts distributed with OpenOCD code. Change automatically created with command sed -i 's/^interface /adapter driver /' $(find tcl/ -type f) Change-Id: I2291dfb96e164beecbeb3366ce83f9df2ad6c197 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5283 Reviewed-by: Marc Schink <dev@zapb.de> Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2019-08-23 08:49:58 -05:00
adapter driver ftdi
tcl/board: add support for Kasli Kasli is an open hardware FPGA board. It is part of the Sinara family of devices designed to control quantum physics experiments (see Sayma_AMC for other boards already suppported by openocd). Kasli was developed as part of the opticlock project. It features a Xilinx Artix 7 100T FPGA, DDR3 RAM, a clock reconstruction and distribution network, four 6 Gb/s transceiver links (three SFP and one SATA) as well as interfaces to up to 12 Eurocard Extension Modules (EEMs). https://github.com/m-labs/sinara/wiki/Kasli http://www.opticlock.de/en/ Change-Id: I88b5e9f16b79e1e731056c45da6b5e1448d2c0e7 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4341 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-01-15 04:53:48 -06:00
ftdi_device_desc "Quad RS232-HS"
ftdi_vid_pid 0x0403 0x6011
ftdi_channel 0
ftdi_layout_init 0x0008 0x000b
# ftdi_location 1:8
reset_config none
transport select jtag
tcl: replace the deprecated commands with "adapter ..." Avoid annoying "deprecated" messages while running the scripts distributed with OpenOCD code. Change automatically created with commands sed -i 's/adapter_khz/adapter speed/g' $(find tcl/ -type f) sed -i 's/adapter_nsrst_delay/adapter srst delay/g' $(find tcl/ -type f) sed -i 's/adapter_nsrst_assert_width/adapter srst pulse_width/g' $(find tcl/ -type f) Minor indentation issue fixed manually in tcl/board/at91sam9g20-ek.cfg tcl/target/at91sam9260_ext_RAM_ext_flash.cfg Change-Id: I425fd56c0c88cd6b06124621306eeb89166dfe71 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5284 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2019-08-23 08:51:00 -05:00
adapter speed 25000
tcl/board: add support for Kasli Kasli is an open hardware FPGA board. It is part of the Sinara family of devices designed to control quantum physics experiments (see Sayma_AMC for other boards already suppported by openocd). Kasli was developed as part of the opticlock project. It features a Xilinx Artix 7 100T FPGA, DDR3 RAM, a clock reconstruction and distribution network, four 6 Gb/s transceiver links (three SFP and one SATA) as well as interfaces to up to 12 Eurocard Extension Modules (EEMs). https://github.com/m-labs/sinara/wiki/Kasli http://www.opticlock.de/en/ Change-Id: I88b5e9f16b79e1e731056c45da6b5e1448d2c0e7 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4341 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-01-15 04:53:48 -06:00
source [find cpld/xilinx-xc7.cfg]
source [find cpld/jtagspi.cfg]
tcl/fpga/xilinx-xadc.cfg: add support for XADC The 7 Series FPGAs contain an on-chip 12 bit ADC that can probe die temperature, internal power supply rail voltages as well as external voltages. The XADC is available both from fabric as well as through the JTAG TAP. This code implements access throught the JTAG TAP. https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf Change-Id: I6cef4d0244add71749fa28b58a736302151cc4dd Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4395 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-01-29 14:12:37 -06:00
source [find fpga/xilinx-xadc.cfg]
xilinx-dna.cfg: generic tools for reading Xilinx Device DNA Most Xilinx FPGA devices contain an embedded, unique device identifier. The identifier is nonvolatile, permanently programmed into the FPGA, and is unchangeable providing a great serial / tracking number. This commit adds generic support for reading the Xilinx Spartan 6 and 7 Series (Kintex, Artix, Ultrascale) Device DNA. The code is similar to the function in fpga/xilinx-xc6s.cfg for Spartan 6 but the register addresses are different and the logic has been simplified. The code was not placed in xilinx-xc7.cfg. The approach of defining taps in the same file as library code to use them is fundamentally broken on boards that have more than one FPGA or other chips. This commit (like the addition of support for Xilinx XADC) starts to remedy that by splitting library code from board-specific fixed definitions. The support code is sourced in the Kasli and KC705 board support files as it was tested on these boards. Change-Id: Iba559c7c1b7e93e1270535fd9e6650007f3794da Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4396 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-02-05 05:54:29 -06:00
source [find fpga/xilinx-dna.cfg]