58 lines
1.2 KiB
INI
58 lines
1.2 KiB
INI
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# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# Geehy APM32F1x target
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#
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# https://global.geehy.com/MCU
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#
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#
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# APM32F1x devices support JTAG and SWD transport.
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#
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source [find target/swj-dp.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME apm32f1x
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}
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# Work-area is a space in RAM used for flash programming, by default use 4 KiB.
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x1000
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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if { [using_jtag] } {
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set _CPUTAPID 0x4ba00477
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} {
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set _CPUTAPID 0x2ba01477
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}
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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if {[using_jtag]} {
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jtag newtap $_CHIPNAME bs -irlen 5
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}
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
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adapter speed 1000
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to perform a soft reset.
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cortex_m reset_config sysresetreq
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}
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