2022-08-30 15:18:31 -05:00
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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2013-06-19 01:03:17 -05:00
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/***************************************************************************
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* Copyright (C) 2005, 2007 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* Copyright (C) 2010 Spencer Oliver *
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* spen@spen-soft.co.uk *
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***************************************************************************/
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.text
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.syntax unified
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.arch armv7-m
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.thumb
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.thumb_func
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.align 2
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/* input parameters - */
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/* R0 = source address */
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/* R1 = destination address */
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/* R2 = number of writes */
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/* R3 = flash write command */
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/* R4 = constant to mask DQ7 bits */
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/* output parameters - */
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/* R5 = 0x80 ok 0x00 bad */
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/* temp registers - */
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/* R6 = value read from flash to test status */
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/* R7 = holding register */
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/* unlock registers - */
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/* R8 = unlock1_addr */
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/* R9 = unlock1_cmd */
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/* R10 = unlock2_addr */
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/* R11 = unlock2_cmd */
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code:
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ldrh r5, [r0], #2
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strh r9, [r8]
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strh r11, [r10]
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strh r3, [r8]
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strh r5, [r1]
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nop
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busy:
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ldrh r6, [r1]
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eor r7, r5, r6
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ands r7, r4, r7
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bne busy
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subs r2, r2, #1 /* 0x1 */
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beq success
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add r1, r1, #2 /* 0x2 */
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b code
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success:
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mov r5, #128 /* 0x80 */
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b done
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done:
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bkpt #0
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.end
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