riscv-openocd/tcl/board/ampere_qs_mq_2s.cfg

# SPDX-License-Identifier: GPL-2.0-or-later
#
# OpenOCD Board Configuration for Ampere Altra ("Quicksilver") and
# Ampere Altra Max ("Mystique") processors
#
# Copyright (c) 2019-2021, Ampere Computing LLC

# Argument Description
#
# JTAGFREQ
# Set the JTAG clock frequency
# Syntax: -c "set JTAGFREQ {freq_in_khz}"
#
# SYSNAME
# Set the system name
# If not specified, defaults to "qs"
# Syntax: -c "set SYSNAME {qs}"
#
# Life-Cycle State (LCS)
# If not specified, defaults to "Secure LCS"
# LCS=0, "Secure LCS"
# LCS=1, "Chip Manufacturing LCS"
# Syntax: -c "set LCS {0}"
# Syntax: -c "set LCS {1}"
#
# CORELIST_S0, CORELIST_S1
# Specify available physical cores by number
# Example syntax to connect to physical cores 16 and 17 for S0 and S1
# Syntax: -c "set CORELIST_S0 {16 17}"
# Syntax: -c "set CORELIST_S1 {16 17}"
#
# COREMASK_S0_LO, COREMASK_S1_LO
# Specify available physical cores 0-63 by mask
# Example syntax to connect to physical cores 16 and 17 for S0 and S1
# Syntax: -c "set COREMASK_S0_LO {0x0000000000030000}"
# Syntax: -c "set COREMASK_S1_LO {0x0000000000030000}"
#
# COREMASK_S0_HI, COREMASK_S1_HI
# Specify available physical cores 64 and above by mask
# Example syntax to connect to physical cores 94 and 95 for S0 and S1
# Syntax: -c "set COREMASK_S0_HI {0x00000000C0000000}"
# Syntax: -c "set COREMASK_S1_HI {0x00000000C0000000}"
#
# SPLITSMP
# Group all ARMv8 cores per socket into individual SMP sessions
# If not specified, group ARMv8 cores from both sockets into one SMP session
# Syntax: -c "set SPLITSMP {}"
#
# PHYS_IDX
# Enable OpenOCD ARMv8 core target physical indexing
# If not specified, defaults to OpenOCD ARMv8 core target logical indexing
# Syntax: -c "set PHYS_IDX {}"

#
# Configure JTAG speed
#

if { [info exists JTAGFREQ] } {
	adapter speed $JTAGFREQ
} else {
	adapter speed 100
}

#
# Set the system name
#

if { [info exists SYSNAME] } {
	set _SYSNAME $SYSNAME
} else {
	set _SYSNAME qs
}

#
# Configure Board level SMP configuration if necessary
#

if { ![info exists SPLITSMP] } {
	# Group dual chip into a single SMP configuration
	set SMP_STR "target smp"
	set CORE_INDEX_OFFSET 0
	set DUAL_SOCKET_SMP_ENABLED ""
}

#
# Configure Resets
#

jtag_ntrst_delay 100
reset_config trst_only

#
# Configure Targets
#

if { [info exists CORELIST_S0] || [info exists COREMASK_S0_LO] || [info exists COREMASK_S0_HI] || \
     [info exists CORELIST_S1] || [info exists COREMASK_S1_LO] || [info exists COREMASK_S1_HI] } {
	set CHIPNAME ${_SYSNAME}1
	if { [info exists CORELIST_S1] } {
		set CORELIST $CORELIST_S1
	} else {
		if { [info exists COREMASK_S1_LO] } {
			set COREMASK_LO $COREMASK_S1_LO
		} else {
			set COREMASK_LO 0x0
		}

		if { [info exists COREMASK_S1_HI] } {
			set COREMASK_HI $COREMASK_S1_HI
		} else {
			set COREMASK_HI 0x0
		}
	}
	source [find target/ampere_qs_mq.cfg]

	if { [info exists DUAL_SOCKET_SMP_ENABLED] && [info exists PHYS_IDX]} {
		if { [info exists MQ_ENABLE] } {
			set CORE_INDEX_OFFSET 128
		} else {
			set CORE_INDEX_OFFSET 80
		}
	}

	set CHIPNAME ${_SYSNAME}0
	if { [info exists CORELIST_S0] } {
		set CORELIST $CORELIST_S0
	} else {
		if { [info exists COREMASK_S0_LO] } {
			set COREMASK_LO $COREMASK_S0_LO
		} else {
			set COREMASK_LO 0x0
		}

		if { [info exists COREMASK_S0_HI] } {
			set COREMASK_HI $COREMASK_S0_HI
		} else {
			set COREMASK_HI 0x0
		}
	}
	source [find target/ampere_qs_mq.cfg]
} else {
	set CHIPNAME ${_SYSNAME}1
	set COREMASK_LO 0x0
	set COREMASK_HI 0x0
	source [find target/ampere_qs_mq.cfg]

	if { [info exists DUAL_SOCKET_SMP_ENABLED] && [info exists PHYS_IDX]} {
		if { [info exists MQ_ENABLE] } {
			set CORE_INDEX_OFFSET 128
		} else {
			set CORE_INDEX_OFFSET 80
		}
	}

	set CHIPNAME ${_SYSNAME}0
	set COREMASK_LO 0x1
	set COREMASK_HI 0x0
	source [find target/ampere_qs_mq.cfg]
}

if { [info exists DUAL_SOCKET_SMP_ENABLED] } {
	# For dual socket SMP configuration, evaluate the string
	eval $SMP_STR
}