39 lines
1.1 KiB
INI
39 lines
1.1 KiB
INI
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# SPDX-License-Identifier: GPL-2.0-or-later
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# NXP QN908x Cortex-M4F with 128 KiB SRAM
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source [find target/swj-dp.tcl]
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set CHIPNAME qn908x
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set CHIPSERIES qn9080
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if { ![info exists WORKAREASIZE] } {
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set WORKAREASIZE 0x20000
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}
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# SWD IDCODE (Cortex M4).
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set CPUTAPID 0x2ba01477
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swj_newdap $CHIPNAME cpu -irlen 4 -expected-id $CPUTAPID
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dap create $CHIPNAME.dap -chain-position $CHIPNAME.cpu
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set TARGETNAME $CHIPNAME.cpu
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target create $TARGETNAME cortex_m -dap $CHIPNAME.dap
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# SRAM is mapped at 0x04000000.
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$TARGETNAME configure -work-area-phys 0x04000000 -work-area-size $WORKAREASIZE
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# flash bank <name> qn908x <base> <size> 0 0 <target#> [calc_checksum]
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# The base must be set as 0x01000000, and the size parameter is unused.
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set FLASHNAME $CHIPNAME.flash
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flash bank $FLASHNAME qn908x 0x01000000 0 0 0 $TARGETNAME calc_checksum
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# We write directly to flash memory over this adapter interface. For debugging
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# this could in theory be faster (the Core clock on reset is normally at 32MHz),
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# but for flashing 1MHz is more reliable.
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adapter speed 1000
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# Delay on reset line.
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adapter srst delay 200
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cortex_m reset_config sysresetreq
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