101 lines
3.0 KiB
INI
101 lines
3.0 KiB
INI
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# STMicroelectronics STM32MP13x (Single Cortex-A7)
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# http://www.st.com/stm32mp1
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# HLA does not support custom CSW nor AP other than 0
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if { [using_hla] } {
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echo "ERROR: HLA transport cannot work with this target."
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echo "ERROR: To use STLink switch to DAP mode, as in \"board/stm32mp13x_dk.cfg\"."
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shutdown
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}
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source [find target/swj-dp.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32mp13x
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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if { [using_jtag] } {
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set _CPUTAPID 0x6ba00477
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} else {
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set _CPUTAPID 0x6ba02477
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}
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}
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# Chip Level TAP Controller, only in jtag mode
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if { [info exists CLCTAPID] } {
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set _CLCTAPID $CLCTAPID
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} else {
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set _CLCTAPID 0x06501041
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}
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swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4
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if { [using_jtag] } {
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jtag newtap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5
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}
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap -ignore-syspwrupack
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# NOTE: keep ap-num and dbgbase to speed-up examine after reset
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# NOTE: do not change the order of target create
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target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1
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target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
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target create $_CHIPNAME.cpu cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000
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$_CHIPNAME.cpu cortex_a maskisr on
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$_CHIPNAME.cpu cortex_a dacrfixup on
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# interface does not work while srst is asserted
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# this is target specific, valid for every board
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# srst resets the debug unit, behavior equivalent to "srst_pulls_trst"
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reset_config srst_gates_jtag srst_pulls_trst
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adapter speed 5000
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adapter srst pulse_width 200
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# bootrom has an internal timeout of 1 second for detecting the boot flash.
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# wait at least 1 second to guarantee we are out of bootrom
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adapter srst delay 1100
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add_help_text axi_secure "Set secure mode for following AXI accesses"
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proc axi_secure {} {
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$::_CHIPNAME.dap apsel 0
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$::_CHIPNAME.dap apcsw 0x10006000
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}
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add_help_text axi_nsecure "Set non-secure mode for following AXI accesses"
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proc axi_nsecure {} {
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$::_CHIPNAME.dap apsel 0
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$::_CHIPNAME.dap apcsw 0x30006000
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}
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axi_secure
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proc dbgmcu_enable_debug {} {
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# keep clock enabled in low-power
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## catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000004}
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# freeze watchdog 1 and 2 on core halted
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catch {$::_CHIPNAME.ap1 mww 0xe008102c 0x00000004}
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catch {$::_CHIPNAME.ap1 mww 0xe008104c 0x00000008}
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}
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proc toggle_cpu_dbg_claim0 {} {
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# toggle CPU0 DBG_CLAIM[0]
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$::_CHIPNAME.ap1 mww 0xe00d0fa0 1
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$::_CHIPNAME.ap1 mww 0xe00d0fa4 1
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}
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# FIXME: most of handlers below will be removed once reset framework get merged
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$_CHIPNAME.ap1 configure -event reset-deassert-pre {
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adapter deassert srst deassert trst
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catch {dap init}
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catch {$::_CHIPNAME.dap apid 1}
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}
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$_CHIPNAME.cpu configure -event reset-deassert-pre {$::_CHIPNAME.cpu arp_examine}
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$_CHIPNAME.cpu configure -event reset-deassert-post {toggle_cpu_dbg_claim0; dbgmcu_enable_debug}
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$_CHIPNAME.ap1 configure -event examine-start {dap init}
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$_CHIPNAME.ap1 configure -event examine-end {dbgmcu_enable_debug}
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