riscv-openocd/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg

######################################
# Target:    Atmel AT91SAM9260
######################################

source [find target/at91sam9261.cfg]

reset_config trst_and_srst

jtag_rclk 4

adapter_nsrst_delay 200
jtag_ntrst_delay 200

scan_chain
$_TARGETNAME configure -event reset-start {
	# at reset chip runs at 32khz
	jtag_rclk 8
}

$_TARGETNAME configure -event reset-init {at91sam_init}

# Flash configuration
#flash bank <name> cfi <base> <size> <chip width> <bus width> <target>
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME

# Faster memory downloads. This is disabled automatically during
# reset init since all reset init sequences are too short for
# fast memory access
arm7_9 dcc_downloads enable
arm7_9 fast_memory_access enable

proc at91sam_init { } {
	mww 0xfffffd08 0xa5000501         ;# RSTC_MR : enable user reset
	mww 0xfffffd44 0x00008000         ;# WDT_MR : disable watchdog

	mww 0xfffffc20 0x00004001         ;# CKGR_MOR : enable the main oscillator
	sleep 20                          ;# wait 20 ms
	mww 0xfffffc30 0x00000001         ;# PMC_MCKR : switch to main oscillator
	sleep 10                          ;# wait 10 ms
	mww 0xfffffc28 0x2060bf09         ;# CKGR_PLLAR: Set PLLA Register for 198,656MHz
	sleep 20                          ;# wait 20 ms
	mww 0xfffffc30 0x00000101         ;# PMC_MCKR : Select prescaler
	sleep 10                          ;# wait 10 ms
	mww 0xfffffc30 0x00000102         ;# PMC_MCKR : Clock from PLLA is selected
	sleep 10                          ;# wait 10 ms

	# Now run at anything fast... ie: 10mhz!
	jtag_rclk 10000                    ;# Increase JTAG Speed to 6 MHz

	mww 0xffffec00 0x0a0a0a0a         ;# SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
	mww 0xffffec04 0x0b0b0b0b         ;# SMC_PULSE0
	mww 0xffffec08 0x00160016         ;# SMC_CYCLE0
	mww 0xffffec0c 0x00161003         ;# SMC_MODE0

	mww 0xfffff870 0xffff0000         ;# PIO_ASR : Select peripheral function for D15..D31
	mww 0xfffff804 0xffff0000         ;# PIO_PDR : Disable PIO function for D15..D31

	mww 0xffffef1c 0x2                ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM

	mww 0xffffea08 0x85227259         ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
	#mww 0xffffea08 0x85227254         ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks)

	mww 0xffffea00 0x1                ;# SDRAMC_MR : issue a NOP command
	mww 0x20000000 0
	mww 0xffffea00 0x2                ;# SDRAMC_MR : issue an 'All Banks Precharge' command
	mww 0x20000000 0
	mww 0xffffea00 0x4                ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
	mww 0x20000000 0
	mww 0xffffea00 0x4
	mww 0x20000000 0
	mww 0xffffea00 0x4
	mww 0x20000000 0
	mww 0xffffea00 0x4
	mww 0x20000000 0
	mww 0xffffea00 0x4
	mww 0x20000000 0
	mww 0xffffea00 0x4
	mww 0x20000000 0
	mww 0xffffea00 0x4
	mww 0x20000000 0
	mww 0xffffea00 0x4
	mww 0x20000000 0
	mww 0xffffea00 0x3                ;# SDRAMC_MR : issue a 'Load Mode Register' command
	mww 0x20000000 0
	mww 0xffffea00 0x0                ;# SDRAMC_MR : normal mode
	mww 0x20000000 0
	mww 0xffffea04 0x5d2              ;# SDRAMC_TR : Set refresh timer count to 15us
}