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riscv-openocd/tcl/board/iar_lpc1768.cfg

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tcl/board: add SPDX tag For historical reasons, no license information was added to the tcl files. This makes trivial adding the SPDX tag through script: fgrep -rL SPDX tcl/board | while read a;do \ sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n }' $a;done With no specific license information from the author, let's extend the OpenOCD project license GPL-2.0-or-later to the files. Change-Id: Ibcf7da62e842aafd036a78db9ea2b9f11f79af16 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7028 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2022-06-12 16:48:05 -05:00
# SPDX-License-Identifier: GPL-2.0-or-later
LPC1768 updates, IAR board support Fix some issues with the generic LPC1768 config file: - Handle the post-reset clock config: 4 MHz internal RC, no PLL. This affects flash and JTAG clocking. - Remove JTAG adapter config; they don't all support trst_and_srst - Remove the rest of the bogus "reset-init" event handler. - Allow explicit CCLK configuration, instead of assuming 12 MHz; some boards will use 100 Mhz (or the post-reset 4 MHz). - Simplify: rely on defaults for endianness and IR-Capture value - Update some comments too Build on those fixes to make a trivial config for the IAR LPC1768 kickstart board (by Olimex) start working. Also, add doxygen to the lpc2000 flash driver, primarily to note a configuration problem with driver: it wrongly assumes the core clock rate never changes. Configs that are safe for updating flash after "reset halt" will thus often be unsafe later ... e.g. for LPC1768, after switching to use PLL0 at 100 MHz. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-03-02 17:00:14 -06:00
# Board from IAR KickStart Kit for LPC1768
# See www.iar.com and also
# http://www.olimex.com/dev/lpc-1766stk.html
#
cfg: fix lpc17xx regression commit b5a6ba46 broke the following board files, update to new cfg. Change-Id: Ic3b776bd32eb72eae6ad1e130e329268ce9ba71a Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/2384 Tested-by: jenkins
2014-11-20 15:33:42 -06:00
source [find target/lpc17xx.cfg]
LPC1768 updates, IAR board support Fix some issues with the generic LPC1768 config file: - Handle the post-reset clock config: 4 MHz internal RC, no PLL. This affects flash and JTAG clocking. - Remove JTAG adapter config; they don't all support trst_and_srst - Remove the rest of the bogus "reset-init" event handler. - Allow explicit CCLK configuration, instead of assuming 12 MHz; some boards will use 100 Mhz (or the post-reset 4 MHz). - Simplify: rely on defaults for endianness and IR-Capture value - Update some comments too Build on those fixes to make a trivial config for the IAR LPC1768 kickstart board (by Olimex) start working. Also, add doxygen to the lpc2000 flash driver, primarily to note a configuration problem with driver: it wrongly assumes the core clock rate never changes. Configs that are safe for updating flash after "reset halt" will thus often be unsafe later ... e.g. for LPC1768, after switching to use PLL0 at 100 MHz. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-03-02 17:00:14 -06:00
# The chip has just been reset.
#
$_TARGETNAME configure -event reset-init {
# FIXME update the core clock to run at 100 MHz;
# and update JTAG clocking similarly; then
# make CCLK match,
flash probe 0
}