2022-06-12 16:48:05 -05:00
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# SPDX-License-Identifier: GPL-2.0-or-later
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2017-07-15 10:53:37 -05:00
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source [find target/atheros_ar9344.cfg]
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reset_config trst_only separate
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proc ar9344_40mhz_pll_init {} {
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# QCA_PLL_SRIF_CPU_DPLL2_REG
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mww 0xb81161C4 0x13210f00
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# QCA_PLL_SRIF_CPU_DPLL3_REG
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mww 0xb81161C8 0x03000000
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# QCA_PLL_SRIF_DDR_DPLL2_REG
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mww 0xb8116244 0x13210f00
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# QCA_PLL_SRIF_DDR_DPLL3_REG
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mww 0xb8116248 0x03000000
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# QCA_PLL_SRIF_BB_DPLL_BASE_REG
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mww 0xb8116188 0x03000000
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# QCA_PLL_CPU_DDR_CLK_CTRL_REG
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mww 0xb8050008 0x0130001C
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mww 0xb8050008 0x0130001C
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mww 0xb8050008 0x0130001C
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# QCA_PLL_CPU_PLL_CFG_REG
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mww 0xb8050000 0x40021380
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# QCA_PLL_DDR_PLL_CFG_REG
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mww 0xb8050004 0x40815800
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# QCA_PLL_CPU_DDR_CLK_CTRL_REG
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mww 0xb8050008 0x0130801C
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# QCA_PLL_SRIF_CPU_DPLL2_REG
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mww 0xb81161C4 0x10810F00
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mww 0xb81161C0 0x41C00000
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# QCA_PLL_SRIF_CPU_DPLL2_REG
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mww 0xb81161C4 0xD0810F00
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# QCA_PLL_SRIF_CPU_DPLL3_REG
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mww 0xb81161C8 0x03000000
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# QCA_PLL_SRIF_CPU_DPLL2_REG
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mww 0xb81161C4 0xD0800F00
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# QCA_PLL_SRIF_CPU_DPLL3_REG
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mww 0xb81161C8 0x03000000
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# QCA_PLL_SRIF_CPU_DPLL3_REG
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mww 0xb81161C8 0x43000000
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# QCA_PLL_SRIF_CPU_DPLL3_REG
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mww 0xb81161C8 0x030003E8
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# QCA_PLL_SRIF_DDR_DPLL2_REG
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mww 0xb8116244 0x10810F00
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mww 0xb8116240 0x41680000
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# QCA_PLL_SRIF_DDR_DPLL2_REG
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mww 0xb8116244 0xD0810F00
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# QCA_PLL_SRIF_DDR_DPLL3_REG
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mww 0xb8116248 0x03000000
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# QCA_PLL_SRIF_DDR_DPLL2_REG
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mww 0xb8116244 0xD0800F00
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# QCA_PLL_SRIF_DDR_DPLL3_REG
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mww 0xb8116248 0x03000000
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# QCA_PLL_SRIF_DDR_DPLL3_REG
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mww 0xb8116248 0x43000000
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# QCA_PLL_SRIF_DDR_DPLL3_REG
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mww 0xb8116248 0x03000718
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# QCA_PLL_CPU_DDR_CLK_CTRL_REG
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mww 0xb8050008 0x01308018
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mww 0xb8050008 0x01308010
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mww 0xb8050008 0x01308000
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# QCA_PLL_DDR_PLL_DITHER_REG
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mww 0xb8050044 0x78180200
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# QCA_PLL_CPU_PLL_DITHER_REG
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mww 0xb8050048 0x41C00000
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}
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proc ar9344_ddr_init {} {
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# QCA_DDR_CTRL_CFG_REG
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mww 0xb8000108 0x40
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# QCA_DDR_RD_DATA_THIS_CYCLE_REG
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mww 0xb8000018 0xFF
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# QCA_DDR_BURST_REG
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mww 0xb80000C4 0x74444444
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# QCA_DDR_BURST2_REG
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mww 0xb80000C8 0x0222
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# QCA_AHB_MASTER_TOUT_MAX_REG
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mww 0xb80000CC 0xFFFFF
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# QCA_DDR_CFG_REG
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mww 0xb8000000 0xC7D48CD0
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# QCA_DDR_CFG2_REG
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mww 0xb8000004 0x9DD0E6A8
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# QCA_DDR_DDR2_CFG_REG
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mww 0xb80000B8 0x0E59
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# QCA_DDR_CFG2_REG
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mww 0xb8000004 0x9DD0E6A8
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# QCA_DDR_CTRL_REG
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mww 0xb8000010 0x08
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mww 0xb8000010 0x08
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mww 0xb8000010 0x10
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mww 0xb8000010 0x20
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# QCA_DDR_EMR_REG
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mww 0xb800000C 0x02
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# QCA_DDR_CTRL_REG
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mww 0xb8000010 0x02
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# QCA_DDR_MR_REG
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mww 0xb8000008 0x0133
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# QCA_DDR_CTRL_REG
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mww 0xb8000010 0x1
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mww 0xb8000010 0x8
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mww 0xb8000010 0x8
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mww 0xb8000010 0x4
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mww 0xb8000010 0x4
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# QCA_DDR_MR_REG
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mww 0xb8000008 0x33
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# QCA_DDR_CTRL_REG
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mww 0xb8000010 0x1
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# QCA_DDR_EMR_REG
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mww 0xb800000C 0x0382
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# QCA_DDR_CTRL_REG
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mww 0xb8000010 0x2
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# QCA_DDR_EMR_REG
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mww 0xb800000C 0x0402
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# QCA_DDR_CTRL_REG
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mww 0xb8000010 0x2
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# QCA_DDR_REFRESH_REG
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mww 0xb8000014 0x4270
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# QCA_DDR_TAP_CTRL_0_REG
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mww 0xb800001C 0x0e
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# QCA_DDR_TAP_CTRL_1_REG
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mww 0xb8000020 0x0e
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# QCA_DDR_TAP_CTRL_2_REG
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mww 0xb8000024 0x0e
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# QCA_DDR_TAP_CTRL_3_REG
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mww 0xb8000028 0x0e
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}
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$_TARGETNAME configure -event reset-init {
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# mww 0xb806001c 0x1000000
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ar9344_40mhz_pll_init
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sleep 100
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# flash remap
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# SPI_CONTROL_ADDR
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mww 0xbF000004 0x43
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ar9344_ddr_init
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sleep 100
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}
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set ram_boot_address 0xa0000000
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$_TARGETNAME configure -work-area-phys 0x1d000000 -work-area-size 0x1000
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2018-12-26 05:47:11 -06:00
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flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0
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