2022-06-12 16:48:05 -05:00
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# SPDX-License-Identifier: GPL-2.0-or-later
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2012-02-04 20:06:42 -06:00
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# The IMX28EVK eval board has a IMX28 chip
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# Tested on SCH-26241 Rev D board with Olimex ARM-USB-OCD
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# Date: 201-02-01
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# Authors: James Robinson & Fabio Estevam
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source [find target/imx28.cfg]
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$_TARGETNAME configure -event gdb-attach { imx28evk_init }
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$_TARGETNAME configure -event reset-init { imx28evk_init }
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proc imx28evk_init { } {
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halt
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#****************************
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# VDDD setting
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#****************************
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# set VDDD =1.55V =(0.8v + TRIG x 0.025v), TRIG=0x1e
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mww 0x80044010 0x0003F503
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mww 0x80044040 0x0002041E
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#****************************
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# CLOCK set up
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#****************************
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# Power up PLL0 HW_CLKCTRL_PLL0CTRL0
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mww 0x80040000 0x00020000
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# Set up fractional dividers for CPU and EMI - HW_CLKCTRL_FRAC0
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# EMI - first set DIV_EMI to div-by-2 before programming frac divider
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mww 0x800400F0 0x80000002
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# CPU: CPUFRAC=19 480*18/29=454.7MHz, EMI: EMIFRAC=22, (480/2)*18/22=196.4MHz
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mww 0x800401B0 0x92921613
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# Clear the bypass bits for CPU and EMI clocks in HW_CLKCTRL_CLKSEQ_CLR
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mww 0x800401D8 0x00040080
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# HCLK = 227MHz,HW_CLKCTRL_HBUS DIV =0x2
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mww 0x80040060 0x00000002
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#****************************
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# POWER up DCDD_VDDA (DDR2)
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#****************************
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# Now set the voltage level to 1.8V HW_POWER_VDDACTRL bits TRC=0xC
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mww 0x80044050 0x0000270C
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#****************************
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# DDR2 DCDD_VDDA
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#****************************
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# First set up pin muxing and drive strength
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# Ungate module clock and bring out of reset HW_PINCTRL_CTRL_CLR
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mww 0x80018008 0xC0000000
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#****************************
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# EMI PAD setting
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#****************************
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# Set up drive strength for EMI pins
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mww 0x80019B80 0x00030000
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#IOMUXC_SW_PAD_CTL_GRP_CTLDS
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# Set up pin muxing for EMI, HW_PINCTRL_MUXSEL10, 11, 12, 13
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mww 0x800181A8 0xFFFFFFFF
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mww 0x800181B8 0xFFFFFFFF
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mww 0x800181C8 0xFFFFFFFF
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mww 0x800181D8 0xFFFFFFFF
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#** Ungate EMI clock in CCM
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mww 0x800400F0 0x00000002
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#============================================================================
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# DDR Controller Registers
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#============================================================================
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# Manufacturer: Elpida
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# Device Part Number: EDE1116AEBG
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# Clock Freq.: 200MHz
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# Density: 1Gb
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# Chip Selects: 1
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# Number of Banks: 8
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# Row address: 13
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# Column address: 10
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#============================================================================
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mww 0x800E0000 0x00000000
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mww 0x800E0040 0x00000000
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mww 0x800E0054 0x00000000
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mww 0x800E0058 0x00000000
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mww 0x800E005C 0x00000000
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mww 0x800E0060 0x00000000
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mww 0x800E0064 0x00000000
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mww 0x800E0068 0x00010101
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mww 0x800E006C 0x01010101
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mww 0x800E0070 0x000f0f01
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mww 0x800E0074 0x0102020A
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mww 0x800E007C 0x00010101
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mww 0x800E0080 0x00000100
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mww 0x800E0084 0x00000100
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mww 0x800E0088 0x00000000
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mww 0x800E008C 0x00000002
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mww 0x800E0090 0x01010000
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mww 0x800E0094 0x07080403
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mww 0x800E0098 0x06005003
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mww 0x800E009C 0x0A0000C8
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mww 0x800E00A0 0x02009C40
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mww 0x800E00A4 0x0002030C
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mww 0x800E00A8 0x0036B009
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mww 0x800E00AC 0x031A0612
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mww 0x800E00B0 0x02030202
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mww 0x800E00B4 0x00C8001C
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mww 0x800E00C0 0x00011900
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mww 0x800E00C4 0xffff0303
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mww 0x800E00C8 0x00012100
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mww 0x800E00CC 0xffff0303
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mww 0x800E00D0 0x00012100
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mww 0x800E00D4 0xffff0303
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mww 0x800E00D8 0x00012100
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mww 0x800E00DC 0xffff0303
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mww 0x800E00E0 0x00000003
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mww 0x800E00E8 0x00000000
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mww 0x800E0108 0x00000612
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mww 0x800E010C 0x01000f02
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mww 0x800E0114 0x00000200
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mww 0x800E0118 0x00020007
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mww 0x800E011C 0xf4004a27
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mww 0x800E0120 0xf4004a27
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mww 0x800E012C 0x07400300
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mww 0x800E0130 0x07400300
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mww 0x800E013C 0x00000005
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mww 0x800E0140 0x00000000
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mww 0x800E0144 0x00000000
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mww 0x800E0148 0x01000000
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mww 0x800E014C 0x01020408
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mww 0x800E0150 0x08040201
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mww 0x800E0154 0x000f1133
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mww 0x800E015C 0x00001f04
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mww 0x800E0160 0x00001f04
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mww 0x800E016C 0x00001f04
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mww 0x800E0170 0x00001f04
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mww 0x800E0288 0x00010000
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mww 0x800E028C 0x00030404
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mww 0x800E0290 0x00000003
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mww 0x800E02AC 0x01010000
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mww 0x800E02B0 0x01000000
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mww 0x800E02B4 0x03030000
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mww 0x800E02B8 0x00010303
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mww 0x800E02BC 0x01020202
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mww 0x800E02C0 0x00000000
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mww 0x800E02C4 0x02030303
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mww 0x800E02C8 0x21002103
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mww 0x800E02CC 0x00061200
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mww 0x800E02D0 0x06120612
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mww 0x800E02D4 0x04420442
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# Mode register 0 for CS1 and CS0, ok to program CS1 even if not used
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mww 0x800E02D8 0x00000000
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# Mode register 0 for CS2 and CS3, not supported in this processor
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mww 0x800E02DC 0x00040004
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# Mode register 1 for CS1 and CS0, ok to program CS1 even if not used
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mww 0x800E02E0 0x00000000
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# Mode register 1 for CS2 and CS3, not supported in this processor
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mww 0x800E02E4 0x00000000
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# Mode register 2 for CS1 and CS0, ok to program CS1 even if not used
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mww 0x800E02E8 0x00000000
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# Mode register 2 for CS2 and CS3, not supported in this processor
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mww 0x800E02EC 0x00000000
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# Mode register 3 for CS1 and CS0, ok to program CS1 even if not used
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mww 0x800E02F0 0x00000000
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# Mode register 3 for CS2 and CS3, not supported in this processor
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mww 0x800E02F4 0xffffffff
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#** start controller **#
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mww 0x800E0040 0x00000001
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# bit[0]: start
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}
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