riscv-openocd/tcl/target/vd_riscv.cfg

# SPDX-License-Identifier: GPL-2.0-or-later
# Cadence virtual debug interface
# RISCV core

if {![info exists _HARTID]} {
	set _HARTID 0x00
}
if {![info exists _CHIPNAME]} {
	set _CHIPNAME riscv
}
set _TARGETNAME $_CHIPNAME.cpu

target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid $_HARTID

riscv set_reset_timeout_sec 120
riscv set_command_timeout_sec 120
riscv set_mem_access sysbus progbuf