riscv-openocd/tcl/target/zynq_7000.cfg

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#
# Xilinx Zynq-7000 All Programmable SoC
#
# http://www.xilinx.com/products/silicon-devices/soc/zynq-7000/index.htm
#
set _CHIPNAME zynq
set _TARGETNAME $_CHIPNAME.cpu
jtag newtap zynq_pl bs -irlen 6 -ircapture 0x1 -irmask 0x03 \
-expected-id 0x23727093 \
-expected-id 0x13722093 \
-expected-id 0x03727093 \
-expected-id 0x03736093
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4ba00477
target create ${_TARGETNAME}0 cortex_a -chain-position $_CHIPNAME.dap \
-coreid 0 -dbgbase 0x80090000
target create ${_TARGETNAME}1 cortex_a -chain-position $_CHIPNAME.dap \
-coreid 1 -dbgbase 0x80092000
target smp ${_TARGETNAME}0 ${_TARGETNAME}1
adapter_khz 1000
${_TARGETNAME}0 configure -event reset-assert-post "cortex_a dbginit"
${_TARGETNAME}1 configure -event reset-assert-post "cortex_a dbginit"