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riscv-openocd/tcl/target/bcm47xx.cfg

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tcl/target: add SPDX tag For historical reasons, no license information was added to the tcl files. This makes trivial adding the SPDX tag through script: fgrep -rL SPDX tcl/ target| while read a;do \ sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n }' $a;done With no specific license information from the author, let's extend the OpenOCD project license GPL-2.0-or-later to the files. Change-Id: I7b2610300b24cccd07bfa6fb5f1266970d5d3a1b Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7027 Tested-by: jenkins
2022-06-12 16:42:27 -05:00
# SPDX-License-Identifier: GPL-2.0-or-later
tcl: add bcm47xx config and Asus RT-N16 board using it This adds the bcm47xx config with the special undocumented trick to put it into standard EJTAG mode from the mystic "LV mode". The RAM setup is not done as it would require considerable efforts without much practical gain. The only issue I noticed so far is that "reset" doesn't actually reset the chip. Unfortunately, it's unclear how to make it work properly with SRST as OpenOCD asserts it in MIPS-specific code so the device will enter LV mode again but the LV tap is already disabled by that time, so it's not possible to send the magic command again. Anyway, this config is more than enough to "recover" any RT-N16 provided the hardware is not damaged. Change-Id: I0894e339763e6d20d1c93341c597382b479d039b Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/1849 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-12-30 12:26:36 -06:00
echo "Forcing reset_config to none to prevent OpenOCD from pulling SRST after the switch from LV is already performed"
reset_config none
jtag newtap $_CHIPNAME-lv tap -irlen 32 -ircapture 0x1 -irmask 0x1f -expected-id $_LVTAPID -expected-id $_CPUID
jtag configure $_CHIPNAME-lv.tap -event setup "jtag tapenable $_CHIPNAME.cpu"
jtag configure $_CHIPNAME-lv.tap -event tap-disable {}
jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUID -disable
jtag configure $_CHIPNAME.cpu -event tap-enable "switch_lv_to_ejtag"
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME mips_m4k -endian little -chain-position $_TARGETNAME
proc switch_lv_to_ejtag {} {
global _CHIPNAME
poll 0
irscan $_CHIPNAME-lv.tap 0x143ff3a
drscan $_CHIPNAME-lv.tap 32 1
jtag tapdisable $_CHIPNAME-lv.tap
poll 1
}