64 lines
1.9 KiB
INI
64 lines
1.9 KiB
INI
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# SPDX-License-Identifier: GPL-2.0-or-later
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# This contains common configuration for NXP Layerscape chassis generation 3
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if { ![info exists _CPUS] } {
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error "_CPUS must be set to the number of cores"
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}
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jtag newtap $_CHIPNAME dap -irlen 4 -expected-id $_DAP_TAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap
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target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 1
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set _CPU_BASE 0x81000000
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set _CPU_STRIDE 0x100000
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set _CPU_DBGOFF 0x10000
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set _CPU_CTIOFF 0x20000
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set _TARGETS {}
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for {set i 0} {$i < $_CPUS} {incr i} {
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set _BASE [expr {$_CPU_BASE + $_CPU_STRIDE * $i}]
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cti create $_CHIPNAME.cti$i -dap $_CHIPNAME.dap -ap-num 0 \
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-baseaddr [expr {$_BASE + $_CPU_CTIOFF}]
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target create $_CHIPNAME.cpu$i aarch64 -dap $_CHIPNAME.dap \
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-cti $_CHIPNAME.cti$i -dbgbase [expr {$_BASE + $_CPU_DBGOFF}] \
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{*}[expr {$i ? "-coreid $i" : "-rtos hwthread" }]
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lappend _TARGETS $_CHIPNAME.cpu$i
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}
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target smp {*}$_TARGETS
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# Service processor
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target create $_CHIPNAME.sp cortex_a -dap $_CHIPNAME.dap -ap-num 0 -dbgbase 0x80138000
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# Normally you will not need to call this, but if you are using the hard-coded
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# Reset Configuration Word (RCW) you will need to call this manually. The CPU's
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# reset vector is 0, and the boot ROM at that location contains ARMv7-A 32-bit
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# instructions. This will cause the CPU to almost immediately execute an
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# illegal instruction.
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#
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# This code is idempotent; releasing a released CPU has no effect, although it
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# will halt/resume the service processor.
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add_help_text release_cpu "Release a cpu which is held off"
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proc release_cpu {cpu} {
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set RST_BRRL 0x1e60060
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set old [target current]
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targets $::_CHIPNAME.sp
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set not_halted [string compare halted [$::_CHIPNAME.sp curstate]]
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if {$not_halted} {
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halt
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}
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# Release the cpu; it will start executing something bogus
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mem2array regs 32 $RST_BRRL 1
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mww $RST_BRRL [expr {$regs(0) | 1 << $cpu}]
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if {$not_halted} {
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resume
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}
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targets $old
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}
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targets $_CHIPNAME.cpu0
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