2009-09-21 13:48:22 -05:00
|
|
|
if { [info exists CHIPNAME] } {
|
2011-10-29 16:32:17 -05:00
|
|
|
set _CHIPNAME $CHIPNAME
|
2009-09-21 13:48:22 -05:00
|
|
|
} else {
|
2011-10-29 16:32:17 -05:00
|
|
|
set _CHIPNAME pic32mx
|
2008-11-30 16:25:43 -06:00
|
|
|
}
|
|
|
|
|
2009-09-21 13:48:22 -05:00
|
|
|
if { [info exists ENDIAN] } {
|
2011-10-29 16:32:17 -05:00
|
|
|
set _ENDIAN $ENDIAN
|
2009-09-21 13:48:22 -05:00
|
|
|
} else {
|
2011-10-29 16:32:17 -05:00
|
|
|
set _ENDIAN little
|
2008-11-30 16:25:43 -06:00
|
|
|
}
|
|
|
|
|
2011-10-29 16:32:17 -05:00
|
|
|
if { [info exists CPUTAPID] } {
|
2008-11-30 16:25:43 -06:00
|
|
|
set _CPUTAPID $CPUTAPID
|
|
|
|
} else {
|
2009-01-13 05:33:19 -06:00
|
|
|
set _CPUTAPID 0x30938053
|
2008-11-30 16:25:43 -06:00
|
|
|
}
|
|
|
|
|
2010-03-15 04:36:46 -05:00
|
|
|
# default working area is 16384
|
2010-03-08 16:54:18 -06:00
|
|
|
if { [info exists WORKAREASIZE] } {
|
2011-10-29 16:32:17 -05:00
|
|
|
set _WORKAREASIZE $WORKAREASIZE
|
2010-03-08 16:54:18 -06:00
|
|
|
} else {
|
2011-10-29 16:32:17 -05:00
|
|
|
set _WORKAREASIZE 0x4000
|
2010-03-08 16:54:18 -06:00
|
|
|
}
|
|
|
|
|
2010-03-15 10:41:30 -05:00
|
|
|
adapter_nsrst_delay 100
|
2008-07-26 05:32:11 -05:00
|
|
|
jtag_ntrst_delay 100
|
|
|
|
|
|
|
|
#jtag scan chain
|
|
|
|
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
|
2010-03-08 16:54:18 -06:00
|
|
|
jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
|
2008-11-30 16:25:43 -06:00
|
|
|
|
2009-09-04 00:17:03 -05:00
|
|
|
set _TARGETNAME $_CHIPNAME.cpu
|
2008-11-30 16:25:43 -06:00
|
|
|
target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_TARGETNAME
|
2008-07-26 05:32:11 -05:00
|
|
|
|
2010-03-15 04:36:46 -05:00
|
|
|
#
|
|
|
|
# At reset the pic32mx does not allow code execution from RAM
|
|
|
|
# we have to setup the BMX registers to allow this.
|
|
|
|
# One limitation is that we loose the first 2k of RAM.
|
|
|
|
#
|
|
|
|
|
|
|
|
global _PIC32MX_DATASIZE
|
2012-03-12 15:11:29 -05:00
|
|
|
global _WORKAREASIZE
|
2010-03-15 04:36:46 -05:00
|
|
|
set _PIC32MX_DATASIZE 0x800
|
|
|
|
set _PIC32MX_PROGSIZE [expr ($_WORKAREASIZE - $_PIC32MX_DATASIZE)]
|
2009-12-21 11:23:09 -06:00
|
|
|
|
2010-03-15 04:36:46 -05:00
|
|
|
$_TARGETNAME configure -work-area-phys 0xa0000800 -work-area-size $_PIC32MX_PROGSIZE -work-area-backup 0
|
2009-12-21 11:23:09 -06:00
|
|
|
$_TARGETNAME configure -event reset-init {
|
|
|
|
#
|
|
|
|
# from reset the pic32 cannot execute code in ram - enable ram execution
|
|
|
|
# minimum offset from start of ram is 2k
|
|
|
|
#
|
|
|
|
|
2010-03-15 04:36:46 -05:00
|
|
|
global _PIC32MX_DATASIZE
|
2012-03-12 15:11:29 -05:00
|
|
|
global _WORKAREASIZE
|
2010-03-15 04:36:46 -05:00
|
|
|
|
2009-12-21 11:23:09 -06:00
|
|
|
# BMXCON
|
|
|
|
mww 0xbf882000 0x001f0040
|
2012-03-12 15:11:29 -05:00
|
|
|
# BMXDKPBA: 2k kernel data @ 0xa0000000
|
2010-03-15 04:36:46 -05:00
|
|
|
mww 0xbf882010 $_PIC32MX_DATASIZE
|
2012-03-12 15:11:29 -05:00
|
|
|
# BMXDUDBA: 14k kernel program @ 0xa0000800 - (BMXDUDBA - BMXDKPBA)
|
|
|
|
mww 0xbf882020 $_WORKAREASIZE
|
|
|
|
# BMXDUPBA: 0k user program - (BMXDUPBA - BMXDUDBA)
|
|
|
|
mww 0xbf882030 $_WORKAREASIZE
|
2009-12-21 11:23:09 -06:00
|
|
|
}
|
2008-07-26 05:32:11 -05:00
|
|
|
|
2010-05-12 17:04:57 -05:00
|
|
|
set _FLASHNAME $_CHIPNAME.flash0
|
2010-03-08 16:54:18 -06:00
|
|
|
flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
|
2010-05-24 05:43:09 -05:00
|
|
|
# add virtual banks for kseg0 and kseg1
|
|
|
|
flash bank vbank0 virtual 0xbfc00000 0 0 0 $_TARGETNAME $_FLASHNAME
|
|
|
|
flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME
|
|
|
|
|
2010-05-12 17:04:57 -05:00
|
|
|
set _FLASHNAME $_CHIPNAME.flash1
|
2010-03-08 16:54:18 -06:00
|
|
|
flash bank $_FLASHNAME pic32mx 0x1d000000 0 0 0 $_TARGETNAME
|
2010-05-24 05:43:09 -05:00
|
|
|
# add virtual banks for kseg0 and kseg1
|
|
|
|
flash bank vbank2 virtual 0xbd000000 0 0 0 $_TARGETNAME $_FLASHNAME
|
|
|
|
flash bank vbank3 virtual 0x9d000000 0 0 0 $_TARGETNAME $_FLASHNAME
|