riscv-openocd/tcl/target/stm32g4x.cfg

# SPDX-License-Identifier: GPL-2.0-or-later

# script for stm32g4x family

#
# stm32g4 devices support both JTAG and SWD transports.
#
source [find target/swj-dp.tcl]
source [find mem_helper.tcl]

if { [info exists CHIPNAME] } {
	set _CHIPNAME $CHIPNAME
} else {
	set _CHIPNAME stm32g4x
}

set _ENDIAN little

# Work-area is a space in RAM used for flash programming
# Smallest current target has 32kB ram, use 16kB by default to avoid surprises
if { [info exists WORKAREASIZE] } {
	set _WORKAREASIZE $WORKAREASIZE
} else {
	set _WORKAREASIZE 0x4000
}

#jtag scan chain
if { [info exists CPUTAPID] } {
	set _CPUTAPID $CPUTAPID
} else {
	if { [using_jtag] } {
		# See STM Document RM0440
		# Section 46.6.3 - corresponds to Cortex-M4 r0p1
		set _CPUTAPID 0x4ba00477
	} {
		set _CPUTAPID 0x2ba01477
	}
}

swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu

if {[using_jtag]} {
	jtag newtap $_CHIPNAME bs -irlen 5
}

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap

$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
flash bank $_CHIPNAME.otp   stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME

if { [info exists QUADSPI] && $QUADSPI } {
	set a [llength [flash list]]
	set _QSPINAME $_CHIPNAME.qspi
	flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
}

# reasonable default
adapter speed 2000

adapter srst delay 100
if {[using_jtag]} {
	jtag_ntrst_delay 100
}

reset_config srst_nogate

if {![using_hla]} {
	# if srst is not fitted use SYSRESETREQ to
	# perform a soft reset
	cortex_m reset_config sysresetreq
}

$_TARGETNAME configure -event reset-init {
	# CPU comes out of reset with HSION | HSIRDY.
	# Use HSI 16 MHz clock, compliant even with VOS == 2.
	# 1 WS compliant with VOS == 2 and 16 MHz.
	mmw 0x40022000 0x00000001 0x0000000E	;# FLASH_ACR: Latency = 1
	mmw 0x40021000 0x00000100 0x00000000	;# RCC_CR |= HSION
	mmw 0x40021008 0x00000001 0x00000002	;# RCC_CFGR: SW=HSI16
}

$_TARGETNAME configure -event reset-start {
	# Reset clock is HSI (16 MHz)
	adapter speed 2000
}

$_TARGETNAME configure -event examine-end {
	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
	mmw 0xE0042004 0x00000007 0

	# Stop watchdog counters during halt
	# DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
	mmw 0xE0042008 0x00001800 0
}

tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000

lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
	targets $_targetname

	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
	# change this value accordingly to configure trace pins
	# assignment
	mmw 0xE0042004 0x00000020 0
}

$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"