riscv-openocd/tcl/target/esp32c2.cfg

# SPDX-License-Identifier: GPL-2.0-or-later
#

# Source the ESP common configuration file.
source [find target/esp_common.cfg]

# Target specific global variables
set _CHIPNAME 					"riscv"
set _CPUTAPID 					0x0000cc25
set _ESP_ARCH 					"riscv"
set _ONLYCPU					1
set _ESP_SMP_TARGET				0
set _ESP_SMP_BREAK 				0
set _ESP_EFUSE_MAC_ADDR_REG  	0x60008840

# Target specific functions should be implemented for each riscv chips.
proc riscv_wdt_disable { } {
    # Halt event can occur during config phase (before "init" is done).
    # Ignore it since mww commands don't work at that time.
    if { [string compare [command mode] config] == 0 } {
        return
    }

    # Timer Group 0 WDT
    mww 0x6001f064 0x50D83AA1
    mww 0x6001F048 0
    # RTC WDT
    mww 0x6000809C 0x50D83AA1
    mww 0x60008084 0
    # SWD
    mww 0x600080A4 0x8F1D312A
    mww 0x600080A0 0x84B00000
}

proc riscv_soc_reset { } {
	global _RISCV_DMCONTROL

    # This procedure does "digital system reset", i.e. resets
    # all the peripherals except for the RTC block.
    # It is called from reset-assert-post target event callback,
    # after assert_reset procedure was called.
    # Since we need the hart to to execute a write to RTC_CNTL_SW_SYS_RST,
    # temporarily take it out of reset. Save the dmcontrol state before
    # doing so.
    riscv dmi_write $_RISCV_DMCONTROL 0x80000001
    # Trigger the reset
    mww 0x60008000 0x9c00a000
    # Workaround for stuck in cpu start during calibration.
    # By writing zero to TIMG_RTCCALICFG_REG, we are disabling calibration
    mww 0x6001F068 0
    # Wait for the reset to happen
    sleep 10
    poll
    # Disable the watchdogs again
    riscv_wdt_disable

    # Here debugger reads allresumeack and allhalted bits as set (0x330a2)
    # We will clean allhalted state by resuming the core.
    riscv dmi_write $_RISCV_DMCONTROL 0x40000001

    # Put the hart back into reset state. Note that we need to keep haltreq set.
    riscv dmi_write $_RISCV_DMCONTROL 0x80000003
}

proc riscv_memprot_is_enabled { } {
	global _RISCV_ABS_CMD _RISCV_ABS_DATA0

	# PMPADDR 0-1 covers entire valid IRAM range and PMPADDR 2-3 covers entire DRAM region
	# pmpcfg0 holds the configuration for the PMP 0-3 address registers

	# read pmpcfg0 and extract into 8-bit variables.
	riscv dmi_write $_RISCV_ABS_CMD 0x2203a0
	set pmpcfg0 [riscv dmi_read $_RISCV_ABS_DATA0]

	set pmp0cfg [expr {($pmpcfg0 >> (8 * 0)) & 0xFF}]
	set pmp1cfg [expr {($pmpcfg0 >> (8 * 1)) & 0xFF}]
	set pmp2cfg [expr {($pmpcfg0 >> (8 * 2)) & 0xFF}]
	set pmp3cfg [expr {($pmpcfg0 >> (8 * 3)) & 0xFF}]

	# read PMPADDR 0-3
	riscv dmi_write $_RISCV_ABS_CMD 0x2203b0
	set pmpaddr0 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
	riscv dmi_write $_RISCV_ABS_CMD 0x2203b1
	set pmpaddr1 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
	riscv dmi_write $_RISCV_ABS_CMD 0x2203b2
	set pmpaddr2 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
	riscv dmi_write $_RISCV_ABS_CMD 0x2203b3
	set pmpaddr3 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]

	set IRAM_LOW 	0x40380000
	set IRAM_HIGH 	0x403C0000
	set DRAM_LOW 	0x3FCA0000
	set DRAM_HIGH 	0x3FCE0000
	set PMP_RWX     0x07
	set PMP_RW     	0x03

	# The lock bit remains unset during the execution of the 2nd stage bootloader.
	# Thus we do not perform a lock bit check for IRAM and DRAM regions.

	# Check OpenOCD can write and execute from IRAM.
	if {$pmpaddr0 >= $IRAM_LOW && $pmpaddr1 <= $IRAM_HIGH} {
    	if {($pmp0cfg & $PMP_RWX) != 0 || ($pmp1cfg & $PMP_RWX) != $PMP_RWX} {
			return 1
		}
	}

	# Check OpenOCD can read/write entire DRAM region.
	if {$pmpaddr2 >= $DRAM_LOW && $pmpaddr3 <= $DRAM_HIGH} {
    	if {($pmp2cfg & $PMP_RW) != 0 && ($pmp3cfg & $PMP_RW) != $PMP_RW} {
			return 1
		}
	}

	return 0
}

create_esp_target $_ESP_ARCH