riscv-openocd/tcl/target/bl702.cfg

# SPDX-License-Identifier: GPL-2.0-or-later

#
# Bouffalo Labs BL702, BL704 and BL706 target
#
# https://en.bouffalolab.com/product/?type=detail&id=8
#
# Default JTAG pins: (if not changed by eFuse configuration)
# TMS - GPIO0
# TDI - GPIO1
# TCK - GPIO2
# TDO - GPIO9
#

source [find mem_helper.tcl]

transport select jtag

if { [info exists CHIPNAME] } {
	set _CHIPNAME $CHIPNAME
} else {
	set _CHIPNAME bl702
}

jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000e05

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME

riscv set_mem_access sysbus

$_TARGETNAME configure -work-area-phys 0x22020000 -work-area-size 0x10000 -work-area-backup 1

# Internal RC ticks on 32 MHz, so this speed should be safe to use.
adapter speed 4000

# Debug Module's ndmreset resets only Trust Zone Controller, so we need to do SW reset instead.
# CTRL_PWRON_RESET triggers full "power-on like" reset.
# This means that pinmux configuration to access JTAG is reset as well, and configured back early
# in BootROM.
$_TARGETNAME configure -event reset-assert-pre {
	halt

	# Switch clock to internal RC32M
	# In HBN_GLB, set ROOT_CLK_SEL = 0
	mmw 0x4000f030 0x0 0x00000003
	# Wait for clock switch
	sleep 10

	# GLB_REG_BCLK_DIS_FALSE
	mww 0x40000ffc 0x0

	# HCLK is RC32M, so BCLK/HCLK doesn't need divider
	# In GLB_CLK_CFG0, set BCLK_DIV = 0 and HCLK_DIV = 0
	mmw 0x40000000 0x0 0x00FFFF00
	# Wait for clock to stabilize
	sleep 10

	# Do reset
	# In GLB_SWRST_CFG2, clear CTRL_SYS_RESET, CTRL_CPU_RESET and CTRL_PWRON_RESET
	mmw 0x40000018 0x0 0x00000007

	# Since this full software reset resets GPIO pinmux as well, we will lose access
	# to JTAG right away after writing to register. This chip doesn't support abstract
	# memory access, so when this is done by progbuf or sysbus, OpenOCD will fail to read
	# if write was successful or not, and will print error about that. Since receiving of
	# this error is expected, we will turn off log printing for a moment,
	set lvl [lindex [debug_level] 1]
	debug_level -1
	# In GLB_SWRST_CFG2, set CTRL_SYS_RESET, CTRL_CPU_RESET and CTRL_PWRON_RESET to 1
	catch {mmw 0x40000018 0x7 0x0}
	debug_level $lvl
}