riscv-openocd/tcl/target/imx6.cfg

# SPDX-License-Identifier: GPL-2.0-or-later

#
# Freescale i.MX6 series
#
# Supports 6Q 6D 6QP 6DP 6DL 6S 6SL 6SLL
#
# Some imx6 chips have Cortex-A7 or an Cortex-M and need special handling
#

if { [info exists CHIPNAME] } {
   set  _CHIPNAME $CHIPNAME
} else {
   set  _CHIPNAME imx6
}

# CoreSight Debug Access Port
if { [info exists DAP_TAPID] } {
    set _DAP_TAPID $DAP_TAPID
} else {
    set _DAP_TAPID 0x4ba00477
}

jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
        -expected-id $_DAP_TAPID

# SDMA / no IDCODE
jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f

# System JTAG Controller

# List supported SJC TAPIDs from imx reference manuals:
set _SJC_TAPID_6Q   0x0191c01d
set _SJC_TAPID_6D   0x0191e01d
set _SJC_TAPID_6QP  0x3191c01d
set _SJC_TAPID_6DP  0x3191d01d
set _SJC_TAPID_6DL  0x0891a01d
set _SJC_TAPID_6S   0x0891b01d
set _SJC_TAPID_6SL  0x0891f01d
set _SJC_TAPID_6SLL 0x088c201d

# Allow external override of the first SJC TAPID
if { [info exists SJC_TAPID] } {
    set _SJC_TAPID $SJC_TAPID
} else {
    set _SJC_TAPID $_SJC_TAPID_6Q
}

jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
        -ignore-version \
        -expected-id $_SJC_TAPID \
        -expected-id $_SJC_TAPID_6QP \
        -expected-id $_SJC_TAPID_6DP \
        -expected-id $_SJC_TAPID_6D \
        -expected-id $_SJC_TAPID_6DL \
        -expected-id $_SJC_TAPID_6S \
        -expected-id $_SJC_TAPID_6SL \
        -expected-id $_SJC_TAPID_6SLL

# GDB target: Cortex-A9, using DAP, configuring only one core
# Base addresses of cores:
# core 0  -  0x82150000
# core 1  -  0x82152000
# core 2  -  0x82154000
# core 3  -  0x82156000
set _TARGETNAME $_CHIPNAME.cpu.0
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \
        -coreid 0 -dbgbase 0x82150000

# some TCK cycles are required to activate the DEBUG power domain
jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100"

proc imx6_dbginit {target} {
        # General Cortex-A8/A9 debug initialisation
        cortex_a dbginit
}

# Slow speed to be sure it will work
adapter speed 1000
$_TARGETNAME configure -event reset-start { adapter speed 1000 }

$_TARGETNAME configure -event reset-assert-post "imx6_dbginit $_TARGETNAME"