179 lines
5.9 KiB
INI
179 lines
5.9 KiB
INI
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# SPDX-License-Identifier: GPL-2.0-or-later
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# cn9130 -- support for the Marvell Octeon TX2 / CN9130 CPU family
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#
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# henrik.nordstorm@addiva.se, Nov 2023
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME cn9130
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}
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if { [info exists MASTERTAPID] } {
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set _MASTERTAPID $MASTERTAPID
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} else {
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set _MASTERTAPID 0x07025357
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}
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if { [info exists APTAPID] } {
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set _APTAPID $APTAPID
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} else {
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set _APTAPID 0x4ba00477
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}
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if { [info exists SBTAPID] } {
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set _SBTAPID $SBTAPID
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} else {
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set _SBTAPID 0x4ba00477
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}
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if { [info exists CORES] } {
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set _CORES $CORES
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} else {
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set _CORES 4
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}
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# CTI base address should be possible to read from the CoreSight
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# ROM table like how the DBG base address is when not specified.
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if { [info exists CTIBASE] } {
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set _CTIBASE $CTIBASE
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} else {
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set _CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
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}
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# CN9130 is a multi-die chip and has a multi level hierarchical
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# JTAG TAP, where all the DAPs are disabled at reset, requiring
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# both configuration to enable access to the chip DAPs, and a
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# vendor specific bypass IR instruction to access the slave TAPs
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# via the master TAP. In addition there is a number of sample
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# bits that should be ignored.
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#
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# The default BYPASS instruction in the master TAP bypasses the
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# whole chip and not only the master TAP. And similarly on
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# IDCODE the master TAP only responds with it's own ID and
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# bypasses the other TAPs on the chip, while OpenOCD expects
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# ID from all enabled TAPs in the chain.
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# Bootstrap with the default boundary scan oriented TAP configuration
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# where the master,ap,sb TAPs are seen as one big fat TAP, which matches
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# what OpenOCD expects from IDCODE and BYPASS.
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jtag newtap $_CHIPNAME bs -irlen 19 -enable -expected-id $_MASTERTAPID
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# Declare the full JTAG chain, but in disabled state during setup
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jtag newtap $_CHIPNAME sample4 -irlen 1 -disable
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jtag newtap $_CHIPNAME sample3 -irlen 1 -disable
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jtag newtap $_CHIPNAME sample2 -irlen 1 -disable
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jtag newtap $_CHIPNAME ap.cpu -irlen 4 -disable -expected-id $_APTAPID
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jtag newtap $_CHIPNAME ap -irlen 5 -disable
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jtag newtap $_CHIPNAME sample1 -irlen 1 -disable
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jtag newtap $_CHIPNAME sb.cpu -irlen 4 -disable -expected-id $_SBTAPID
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jtag newtap $_CHIPNAME sb -irlen 5 -disable
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jtag newtap $_CHIPNAME master -irlen 5 -disable -ir-bypass 0x11 -expected-id $_MASTERTAPID
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# Once the iniial IDCODE scan has completed switch to more detailed
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# scan chain giving access to the individual chip TAPs.
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jtag configure $_CHIPNAME.bs -event setup "cn9130_enable_full_chain $_CHIPNAME"
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proc cn9130_enable_full_chain { _CHIPNAME } {
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# Switch to detailed TAP declaration
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jtag tapdisable $_CHIPNAME.bs
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jtag tapenable $_CHIPNAME.master
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jtag tapenable $_CHIPNAME.sb
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jtag tapenable $_CHIPNAME.sample1
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jtag tapenable $_CHIPNAME.ap
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jtag tapenable $_CHIPNAME.sample2
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jtag tapenable $_CHIPNAME.sample3
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jtag tapenable $_CHIPNAME.sample4
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}
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# AP & SB TAPs have a config register to enable/disable access to
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# the auxilary DAP TAP. Default off which hides the DAP TAP from
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# the scan chain.
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proc cn9130_dap_config { chip tap state } {
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irscan $chip.$tap 0x12
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drscan $chip.$tap 32 $state
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}
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jtag configure $_CHIPNAME.bs -event tap-disable ""
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jtag configure $_CHIPNAME.bs -event tap-enable ""
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jtag configure $_CHIPNAME.sample4 -event tap-enable ""
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jtag configure $_CHIPNAME.sample3 -event tap-enable ""
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jtag configure $_CHIPNAME.sample2 -event tap-enable ""
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jtag configure $_CHIPNAME.ap.cpu -event tap-disable "cn9130_dap_config $_CHIPNAME ap 0"
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jtag configure cn9130.ap.cpu -event tap-enable "cn9130_dap_config $_CHIPNAME ap 1"
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jtag configure $_CHIPNAME.ap -event tap-enable ""
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jtag configure $_CHIPNAME.sample1 -event tap-enable ""
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jtag configure $_CHIPNAME.sb.cpu -event tap-disable "cn9130_dap_config $_CHIPNAME sb 0"
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jtag configure cn9130.sb.cpu -event tap-enable "cn9130_dap_config $_CHIPNAME sb 1"
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jtag configure $_CHIPNAME.sb -event tap-enable ""
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jtag configure $_CHIPNAME.master -event tap-enable ""
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dap create $_CHIPNAME.ap.dap -chain-position $_CHIPNAME.ap.cpu
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# Main bus
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target create $_CHIPNAME.ap.axi mem_ap \
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-dap $_CHIPNAME.ap.dap \
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-ap-num 0
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# Periperials bus
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target create $_CHIPNAME.ap.apb mem_ap \
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-dap $_CHIPNAME.ap.dap \
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-ap-num 1
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# MSS bus
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target create $_CHIPNAME.ap.ahb mem_ap \
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-dap $_CHIPNAME.ap.dap \
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-ap-num 2
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# AP A72 CPU cores
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set _smp_command ""
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for { set _core 0 } { $_core < $_CORES } { incr _core 1 } {
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cti create $_CHIPNAME.ap.cti.$_core \
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-dap $_CHIPNAME.ap.dap \
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-baseaddr [ lindex $_CTIBASE $_core ] \
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-ap-num 1
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if { $_core == 0 } {
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target create $_CHIPNAME.ap.a72.$_core aarch64 \
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-dap $_CHIPNAME.ap.dap \
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-ap-num 1 \
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-cti $_CHIPNAME.ap.cti.$_core \
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-coreid $_core \
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-rtos hwthread
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set _smp_command "target smp $_CHIPNAME.ap.a72.$_core"
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} else {
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# Defer non-boot cores. Held hard in reset until
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# SMP is activated.
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target create $_CHIPNAME.ap.a72.$_core aarch64 \
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-dap $_CHIPNAME.ap.dap \
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-ap-num 1 \
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-cti $_CHIPNAME.ap.cti.$_core \
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-coreid $_core \
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-defer-examine
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set _smp_command "$_smp_command $_CHIPNAME.ap.a72.$_core"
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}
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}
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# Set up the A72 cluster as SMP
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# Note: Only the boot core is active by default. The other core DAPs can
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# be enabled by arp_examine after they have been released from hard reset.
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eval $_smp_command
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# AP MSS M3 CPU core. Defer as it is held in reset until firmware is loaded.
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target create $_CHIPNAME.ap.mss cortex_m -dap $_CHIPNAME.ap.dap -ap-num 2 -defer-examine
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# Why is this needed? reset fails with "Debug regions are unpowered" otherwise
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$_CHIPNAME.ap.axi configure -event examine-start "dap init"
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# Automate enabling the AP A72 DAP once the full scan chain is enabled
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proc cn9130_ap_setup { _CHIPNAME } {
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jtag tapenable $_CHIPNAME.ap.cpu
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targets $_CHIPNAME.ap.a72.0
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}
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jtag configure $_CHIPNAME.ap -event setup "cn9130_ap_setup $_CHIPNAME"
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