2022-06-12 16:42:27 -05:00
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# SPDX-License-Identifier: GPL-2.0-or-later
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2019-04-04 14:25:49 -05:00
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#
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# Freescale i.MX6SoloX
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#
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME imx6sx
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}
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# 2x CoreSight Debug Access Port for Cortex-M4 and Cortex-A9
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if { [info exists DAP_TAPID] } {
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set _DAP_TAPID $DAP_TAPID
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} else {
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set _DAP_TAPID 0x4ba00477
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}
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jtag newtap $_CHIPNAME cpu_m4 -irlen 4 -ircapture 0x01 -irmask 0x0f \
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-expected-id $_DAP_TAPID
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dap create $_CHIPNAME.dap_m4 -chain-position $_CHIPNAME.cpu_m4
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jtag newtap $_CHIPNAME cpu_a9 -irlen 4 -ircapture 0x01 -irmask 0x0f \
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-expected-id $_DAP_TAPID
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dap create $_CHIPNAME.dap_a9 -chain-position $_CHIPNAME.cpu_a9
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# SDMA / no IDCODE
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jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f
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# System JTAG Controller
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if { [info exists SJC_TAPID] } {
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set _SJC_TAPID $SJC_TAPID
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} else {
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set _SJC_TAPID 0x0891c01d
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}
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jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
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-expected-id $_SJC_TAPID -ignore-version
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# Cortex-A9 (boot core)
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target create $_CHIPNAME.cpu_a9 cortex_a -dap $_CHIPNAME.dap_a9 \
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-coreid 0 -dbgbase 0x82150000
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# Cortex-M4 (default off)
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target create $_CHIPNAME.cpu_m4 cortex_m -dap $_CHIPNAME.dap_m4 \
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-ap-num 0 -defer-examine
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# AHB mem-ap target
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target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap_a9 -ap-num 0
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# Default target is Cortex-A9
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targets $_CHIPNAME.cpu_a9
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