ki5_update
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(kicad_pcb (version 20171130) (host pcbnew 5.0.0-rc3-6a2723a~65~ubuntu16.04.1)
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(general
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(thickness 1.3)
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(thickness 1.6)
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(drawings 9)
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(tracks 44438)
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(zones 0)
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@ -26719,7 +26719,7 @@
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(segment (start 94.95 153.475) (end 95.325 153.85) (width 0.254) (layer B.Cu) (net 1))
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(segment (start 94.95 152.2189) (end 95.3477 151.8212) (width 0.254) (layer F.Cu) (net 1))
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(segment (start 94.95 153.475) (end 94.95 152.2189) (width 0.254) (layer F.Cu) (net 1))
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(via (at 97.35 153.475) (size 0.3556) (drill 0.2032) (layers F.Cu B.Cu) (net 1))
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(via (at 97.35 153.475) (size 0.3556) (drill 0.2032) (layers F.Cu B.Cu) (net 1) (status 1000000))
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(segment (start 97.725 153.85) (end 97.35 153.475) (width 0.254) (layer B.Cu) (net 1))
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(segment (start 97.3506 153.475) (end 97.7292 153.8536) (width 0.254) (layer F.Cu) (net 1))
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(segment (start 97.35 153.475) (end 97.3506 153.475) (width 0.254) (layer F.Cu) (net 1))
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9230
kicad/Ki5.net
9230
kicad/Ki5.net
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Load Diff
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EESchema Schematic File Version 4
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LIBS:Ki5-cache
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EELAYER 26 0
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EELAYER END
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$Descr B 17000 11000
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@ -1888,17 +1889,6 @@ Wire Wire Line
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11005 1750 12150 1750
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Wire Wire Line
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11005 2150 12250 2150
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$Comp
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L Transistor_FET:FDG6335N Q5
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U 2 1 5CD93B12
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P 3200 5100
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F 0 "Q5" H 3110 5330 50 0000 L CNN
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F 1 "FDG6335N" H 2875 5255 50 0000 L CNN
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F 2 "Package_TO_SOT_SMD:SOT-363_SC-70-6" H 3400 5025 50 0001 L CIN
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F 3 "http://www.gneic.com/product/datasheet/FDG6335N-1122853.pdf" H 3200 5100 50 0001 L CNN
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2 3200 5100
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1 0 0 -1
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$EndComp
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Wire Wire Line
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2800 4800 3300 4800
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Wire Wire Line
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@ -2162,4 +2152,15 @@ Wire Wire Line
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Wire Wire Line
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10705 2650 12250 2650
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Connection ~ 10705 2650
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$Comp
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L Transistor_FET:IRLML2060 Q5
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U 1 1 5C724162
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P 3200 5100
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F 0 "Q5" H 3100 5350 50 0000 L CNN
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F 1 "IRLML2060" H 2800 5250 50 0000 L CNN
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F 2 "Package_TO_SOT_SMD:SOT-23" H 3400 5025 50 0001 L CIN
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F 3 "https://www.infineon.com/dgdl/irlml2060pbf.pdf?fileId=5546d462533600a401535664b7fb25ee" H 3200 5100 50 0001 L CNN
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1 3200 5100
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1 0 0 -1
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$EndComp
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$EndSCHEMATC
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