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riscv / OpenFPGA
Verilog
0
0
fpga
fpga-soc
Updated
2024-12-03 01:41:32 -06:00
skywater / ethernet
Verilog
0
0
WIP 100BASE-TX PHY
Updated
2024-12-02 20:55:12 -06:00
riscv / caravel
Verilog
0
0
magic
yosys
caravel
picorv32
openroad
openram
sky130
Updated
2024-11-04 10:25:41 -06:00